//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/******************************************************************************
**
**  COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be construed as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       xllp_ucb1400.h
**
**  PURPOSE: contains all UCB1400 specific macros, typedefs, and prototypes.
**           Declares no storage.
**                  
**
******************************************************************************/
#ifndef __XLLP_UCB1400_H__
#define __XLLP_UCB1400_H__
#include "xllp_acodec.h"
// UCB1400, Philips proprietary.
#define    XLLP_AC97_CR_U14_IO_CTRL_STAT  0x5A  // I/O pin level [0..9]. R/W.
#define    XLLP_AC97_CR_U14_IO_DIRN       0x5C  // Sets In(0) or Out(1) for I/O pins
#define    XLLP_AC97_CR_U14_POS_INT_ENAB  0x5E  // Enables intrpt sgnl on rising edge
#define    XLLP_AC97_CR_U14_NEG_INT_ENAB  0x60  // Enables intrpt sgnl on falling edge
#define    XLLP_AC97_CR_U14_INT_CLR_STAT  0x62  // Reports intrpt status, W clears stat
#define    XLLP_AC97_CR_U14_TS_CTRL       0x64  // Touch Screen Control
#define    XLLP_AC97_CR_U14_ADC_CTRL      0x66  // ADC Control
#define    XLLP_AC97_CR_U14_ADC_DATA      0x68  // ADC Data
#define    XLLP_AC97_CR_U14_FTR_CTRL_STAT1  0x6A  // Feature control + status reg 1
#define    XLLP_AC97_CR_U14_FTR_CTRL_STAT2  0x6C  // Feature control + status reg 2
#define    XLLP_AC97_CR_U14_TEST_CTRL       0x6E  // Only in Vendor Specific Test Mode

#define    XLLP_AC97_U14_RR_LOUDNESS ( 0x1 << 5 )    // Loudness (bass boost) supported
#define    XLLP_AC97_U14_RR_20BITDAC ( 0x1 << 7 )    // supports 20 bit DAC
#define XLLP_AC97_U14_RR_20BITADC ( 0x1 << 9 )    // supports 20 bit ADC

// Master Volume Register (MVR) definitions

#define XLLP_AC97_U14_MVR_MR_SHIFT    0               // Volume Right, 6 bits wide
// Bits 6,7 Reserved
#define XLLP_AC97_U14_MVR_ML_SHIFT    8               // Volume Left, 6 bits wide
// Bit 14 Reserved
#define XLLP_AC97_U14_MVR_MM          ( 0x1 << 15 )   // Master Mute

// MIC Volume Register (MCVR) definitions

// Bits 0-5 Reserved
#define XLLP_AC97_U14_MCVR_20DB       ( 0x1 << 6 )    // MIC Volume boosted by 20 dB
// Bits 7-15 Reserved

// Record Select Register (RSR) definitions

#define XLLP_AC97_U14_RSR_SR_SHIFT    0
#define XLLP_AC97_U14_RSR_SR_CL       ( 0x0 << XLLP_AC97_U14_RSR_SR_SHIFT ) // copy from left
#define XLLP_AC97_U14_RSR_SR_LINE     ( 0x100 << XLLP_AC97_U14_RSR_SR_SHIFT )

#define XLLP_AC97_U14_RSR_SL_SHIFT    8
#define XLLP_AC97_U14_RSR_SL_MIC      ( 0x0 << XLLP_AC97_U14_RSR_SL_SHIFT )
#define XLLP_AC97_U14_RSR_SL_LINE     ( 0x100 << XLLP_AC97_U14_RSR_SL_SHIFT )

// Record Gain Register (RGR) definitions

#define XLLP_AC97_U14_RGR_GR_SHIFT    0               // Gain Right, 4 bits wide
// Bits 4-7 Reserved
#define XLLP_AC97_U14_RGR_GL_SHIFT    8               // Gain Left, 4 bits wide
// Bits 12-14 Reserved
#define XLLP_AC97_U14_RGR_RM          ( 0x1 << 15 )   // Record Mute

// General Purpose Register (GPR) definitions

// Bits 0-6 Reserved
#define XLLP_AC97_U14_GPR_LPBK        ( 0x1 << 7 )    // ADC/DAC Loopback Mode
// Bits 8-15 Reserved

// Powerdown Control/Status Register (PCSR) definitions

#define XLLP_AC97_U14_PCSR_ADCR   ( 0x1 << 0 )    // ADC ready to transmit data
#define XLLP_AC97_U14_PCSR_DAC    ( 0x1 << 1 )    // DAC ready to accept data
// Bit 2 Reserved
#define XLLP_AC97_U14_PCSR_REF    ( 0x1 << 3 )    // Vref is up to nominal level
// Bits 4-7 Reserved
#define XLLP_AC97_U14_PCSR_PR0    ( 0x1 << 8 )    // ADC & input path powerdown
#define XLLP_AC97_U14_PCSR_PR1    ( 0x1 << 9 )    // DAC & ouput path powerdown
// Bit 10 Reserved
#define XLLP_AC97_U14_PCSR_PR3    ( 0x1 << 11 )   // Vref powerdown
#define XLLP_AC97_U14_PCSR_PR4    ( 0x1 << 12 )   // Digital interface powerdown
#define XLLP_AC97_U14_PCSR_PR5    ( 0x1 << 13 )   // Internal Clock disable
// Bits 14,15 Reserved

// Extended Audio ID Register (EAIDR) definitions

#define XLLP_AC97_U14_EAIDR_VRA   ( 0x1 << 0 )    // Variable Rate PCM Audio supported
// Bits 1-13 Reserved
#define XLLP_AC97_U14_EAIDR_ID    ( 0x11 << 14 )  // 2 bits wide, Always 0.  UCB1400 is a primary codec

// Extended Audio Status and Control Register (EASCR) definitions

#define XLLP_AC97_U14_EASCR_VRA   ( 0x1 << 0 )    // Enable Variable Rate Audio mode
// Bits 1-15 Reserved

// Audio DAC & ADC Sample Rate Control Register (ADR & AAR) definitions

#define XLLP_AC97_U14_DR_8000     0x1F40  //  8000 samples/sec
#define XLLP_AC97_U14_DR_11025    0x2B11  // 11025 samples/sec
#define XLLP_AC97_U14_DR_16000    0x3E80  // 16000 samples/sec
#define XLLP_AC97_U14_DR_22050    0x5622  // 22050 samples/sec
#define XLLP_AC97_U14_DR_32000    0x7D00  // 32000 samples/sec
#define XLLP_AC97_U14_DR_44100    0xAC44  // 44100 samples/sec
#define XLLP_AC97_U14_DR_48000    0xBB80  // 48000 samples/sec

// I/O Data Register (IODR) and I/O Data Direction (IODIRR) definitions
#define XLLP_AC97_U14_IO0 ( 0x1 << 0 )
#define XLLP_AC97_U14_IO1 ( 0x1 << 1 )
#define XLLP_AC97_U14_IO2 ( 0x1 << 2 )
#define XLLP_AC97_U14_IO3 ( 0x1 << 3 )
#define XLLP_AC97_U14_IO4 ( 0x1 << 4 )
#define XLLP_AC97_U14_IO5 ( 0x1 << 5 )
#define XLLP_AC97_U14_IO6 ( 0x1 << 6 )
#define XLLP_AC97_U14_IO7 ( 0x1 << 7 )
#define XLLP_AC97_U14_IO8 ( 0x1 << 8 )
#define XLLP_AC97_U14_IO9 ( 0x1 << 9 )
// Bits 10-15 Reserved

// Positive INT Enable Register (PIER) definitions

#define XLLP_AC97_U14_PIER_ION0   ( 0x1 << 0 )    // enable falling edge interrupt for I/O pin 0
#define XLLP_AC97_U14_PIER_ION1   ( 0x1 << 1 )    // enable falling edge interrupt for I/O pin 1
#define XLLP_AC97_U14_PIER_ION2   ( 0x1 << 2 )    // enable falling edge interrupt for I/O pin 2
#define XLLP_AC97_U14_PIER_ION3   ( 0x1 << 3 )    // enable falling edge interrupt for I/O pin 3

#define XLLP_AC97_U14_PIER_ION4   ( 0x1 << 4 )    // enable falling edge interrupt for I/O pin 4
#define XLLP_AC97_U14_PIER_ION5   ( 0x1 << 5 )    // enable falling edge interrupt for I/O pin 5
#define XLLP_AC97_U14_PIER_ION6   ( 0x1 << 6 )    // enable falling edge interrupt for I/O pin 6
#define XLLP_AC97_U14_PIER_ION7   ( 0x1 << 7 )    // enable falling edge interrupt for I/O pin 7

#define XLLP_AC97_U14_PIER_ION8   ( 0x1 << 8 )    // enable falling edge interrupt for I/O pin 8
#define XLLP_AC97_U14_PIER_ION9   ( 0x1 << 9 )    // enable falling edge interrupt for I/O pin 9
#define XLLP_AC97_U14_PIER_D10    ( 0x1 << 10 )   // Reserved
#define XLLP_AC97_U14_PIER_ADCP   ( 0x1 << 11 )   // enable falling edge interrupt for ADC Ready

#define XLLP_AC97_U14_PIER_TPXP   ( 0x1 << 12 )   // enable falling edge interrupt for TSPX
#define XLLP_AC97_U14_PIER_TMXP   ( 0x1 << 13 )   // enable falling edge interrupt for TSMX
#define XLLP_AC97_U14_PIER_D14    ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_PIER_OVLP   ( 0x1 << 15 )   // enable falling edge interrupt for OVFL

// Negative INT Enable Register (NIER) definitions

#define XLLP_AC97_U14_NIER_ION0   ( 0x1 << 0 )    // enable falling edge interrupt for I/O pin 0
#define XLLP_AC97_U14_NIER_ION1   ( 0x1 << 1 )    // enable falling edge interrupt for I/O pin 1
#define XLLP_AC97_U14_NIER_ION2   ( 0x1 << 2 )    // enable falling edge interrupt for I/O pin 2
#define XLLP_AC97_U14_NIER_ION3   ( 0x1 << 3 )    // enable falling edge interrupt for I/O pin 3

#define XLLP_AC97_U14_NIER_ION4   ( 0x1 << 4 )    // enable falling edge interrupt for I/O pin 4
#define XLLP_AC97_U14_NIER_ION5   ( 0x1 << 5 )    // enable falling edge interrupt for I/O pin 5
#define XLLP_AC97_U14_NIER_ION6   ( 0x1 << 6 )    // enable falling edge interrupt for I/O pin 6
#define XLLP_AC97_U14_NIER_ION7   ( 0x1 << 7 )    // enable falling edge interrupt for I/O pin 7

#define XLLP_AC97_U14_NIER_ION8   ( 0x1 << 8 )    // enable falling edge interrupt for I/O pin 8
#define XLLP_AC97_U14_NIER_ION9   ( 0x1 << 9 )    // enable falling edge interrupt for I/O pin 9
#define XLLP_AC97_U14_NIER_D10    ( 0x1 << 10 )   // Reserved
#define XLLP_AC97_U14_NIER_ADCN   ( 0x1 << 11 )   // enable falling edge interrupt for ADC Ready

#define XLLP_AC97_U14_NIER_TPXN   ( 0x1 << 12 )   // enable falling edge interrupt for TSPX
#define XLLP_AC97_U14_NIER_TMXN   ( 0x1 << 13 )   // enable falling edge interrupt for TSMX
#define XLLP_AC97_U14_NIER_D14    ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_NIER_OVLN   ( 0x1 << 15 )   // enable falling edge interrupt for OVFL

// INT Clear/Status Register (ICSR) definitions

#define XLLP_AC97_U14_ICSR_IOS0   ( 0x1 << 0 )    // use to check or clear the int status for IO Bit 0
#define XLLP_AC97_U14_ICSR_IOS1   ( 0x1 << 1 )    // use to check or clear the int status for IO Bit 1
#define XLLP_AC97_U14_ICSR_IOS2   ( 0x1 << 2 )    // use to check or clear the int status for IO Bit 2
#define XLLP_AC97_U14_ICSR_IOS3   ( 0x1 << 3 )    // use to check or clear the int status for IO Bit 3

#define XLLP_AC97_U14_ICSR_IOS4   ( 0x1 << 4 )    // use to check or clear the int status for IO Bit 4
#define XLLP_AC97_U14_ICSR_IOS5   ( 0x1 << 5 )    // use to check or clear the int status for IO Bit 5
#define XLLP_AC97_U14_ICSR_IOS6   ( 0x1 << 6 )    // use to check or clear the int status for IO Bit 6
#define XLLP_AC97_U14_ICSR_IOS7   ( 0x1 << 7 )    // use to check or clear the int status for IO Bit 7

#define XLLP_AC97_U14_ICSR_IOS8   ( 0x1 << 8 )    // use to check or clear the int status for IO Bit 8
#define XLLP_AC97_U14_ICSR_IOS9   ( 0x1 << 9 )    // use to check or clear the int status for IO Bit 9
#define XLLP_AC97_U14_ICSR_D10    ( 0x1 << 10 )   // Reserved
#define XLLP_AC97_U14_ICSR_ADCS   ( 0x1 << 11 )   // use to check or clear the int status for ADC ready

#define XLLP_AC97_U14_ICSR_TSPX   ( 0x1 << 12 )   // use to check or clear the int status for TSPX
#define XLLP_AC97_U14_ICSR_TSMX   ( 0x1 << 13 )   // use to check or clear the int status for TSMX
#define XLLP_AC97_U14_ICSR_D14    ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_ICSR_OVLS   ( 0x1 << 15 )   // use to check or clear the int status for OVFL

// Touch Screen Control Register (TSCR) defintions

#define XLLP_AC97_U14_TSCR_TSMX_POW   ( 0x1 << 0 )    // TSMX pin is powered
#define XLLP_AC97_U14_TSCR_TSPX_POW   ( 0x1 << 1 )    // TSPX pin is powered
#define XLLP_AC97_U14_TSCR_TSMY_POW   ( 0x1 << 2 )    // TSMY pin is powered
#define XLLP_AC97_U14_TSCR_TSPY_POW   ( 0x1 << 3 )    // TSPY pin is powered

#define XLLP_AC97_U14_TSCR_TSMX_GND   ( 0x1 << 4 )    // TSMX pin is grounded
#define XLLP_AC97_U14_TSCR_TSPX_GND   ( 0x1 << 5 )    // TSPX pin is grounded
#define XLLP_AC97_U14_TSCR_TSMY_GND   ( 0x1 << 6 )    // TSMY pin is grounded
#define XLLP_AC97_U14_TSCR_TSPY_GND   ( 0x1 << 7 )    // TSPY pin is grounded

#define XLLP_AC97_U14_TSCR_INTMO      ( 0x0 << 8 )    // Interrupt Mode
#define XLLP_AC97_U14_TSCR_PREMO      ( 0x1 << 8 )    // Pressure Measurement Mode
#define XLLP_AC97_U14_TSCR_POSMO      ( 0x2 << 8 )    // Position Measurement Mode
#define XLLP_AC97_U14_TSCR_HYSD       ( 0x1 << 10 )   // Hysteresis deactivated
#define XLLP_AC97_U14_TSCR_BIAS       ( 0x1 << 11 )   // Bias circuitry activated

#define XLLP_AC97_U14_TSCR_PX         ( 0x1 << 12 )   // Inverted state of TSPX pin
#define XLLP_AC97_U14_TSCR_MX         ( 0x1 << 13 )   // Inverted state of TSMX pin
#define XLLP_AC97_U14_TSCR_D14        ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_TSCR_D15        ( 0x1 << 15 )   // Reserved

// ADC Control Register (ADCCR) definitions

#define XLLP_AC97_U14_ADCCR_ASE       ( 0x1 << 0 ) // ADC is armed by AS bit and started by rising edge on ADCSYNC pin
#define XLLP_AC97_U14_ADCCR_D1        ( 0x1 << 1 ) // Reserved

#define XLLP_AC97_U14_ADCCR_AI_SHIFT  2
#define XLLP_AC97_U14_ADCCR_AI_TSPX   ( 0x0 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSPX
#define XLLP_AC97_U14_ADCCR_AI_TSMX   ( 0x1 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSMX
#define XLLP_AC97_U14_ADCCR_AI_TSPY   ( 0x2 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSPY
#define XLLP_AC97_U14_ADCCR_AI_TSMY   ( 0x3 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSMY
#define XLLP_AC97_U14_ADCCR_AI_AD0    ( 0x4 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD0
#define XLLP_AC97_U14_ADCCR_AI_AD1    ( 0x5 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD1
#define XLLP_AC97_U14_ADCCR_AI_AD2    ( 0x6 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD2
#define XLLP_AC97_U14_ADCCR_AI_AD3    ( 0x7 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD3

#define XLLP_AC97_U14_ADCCR_D5        ( 0x1 << 5 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D6        ( 0x1 << 6 )    // Reserved
#define XLLP_AC97_U14_ADCCR_AS        ( 0x1 << 7 )    // Start the ADC conversion seq.

#define XLLP_AC97_U14_ADCCR_D8        ( 0x1 << 8 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D9        ( 0x1 << 9 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D10       ( 0x1 << 10 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D11       ( 0x1 << 11 )   // Reserved

#define XLLP_AC97_U14_ADCCR_D12       ( 0x1 << 12 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D13       ( 0x1 << 13 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D14       ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_ADCCR_AE        ( 0x1 << 15 )   // ADC is activated

// ADC Data Register (ADCDR) definitions

#define XLLP_AC97_U14_ADCDR_MASK      0x3FF           // ADC data register data mask
#define XLLP_AC97_U14_ADCDR_ADV       ( 0x1 << 15 )   // Conversion complete

// Feature Control/Status Register 1 (FCSR1) definitions

#define XLLP_AC97_U14_FCSR1_OVFL      ( 0x1 << 0 )    // ADC overflow status
// bit 1 is reserved
#define XLLP_AC97_U14_FCSR1_GIEN      ( 0x1 << 2 )    // Enable interrupt/wakeup signaling
#define XLLP_AC97_U14_FCSR1_HIPS      ( 0x1 << 3 )    // Activate ADC High Pass Filter
#define XLLP_AC97_U14_FCSR1_DC        ( 0x1 << 4 )    // DC filter is enabled
#define XLLP_AC97_U14_FCSR1_DE        ( 0x1 << 5 )    // De-emphasis is enabled
#define XLLP_AC97_U14_FCSR1_XTM       ( 0x1 << 6 )    // Crystal Oscillator Powerdown Mode

#define XLLP_AC97_U14_FCSR1_M_SHIFT   7
#define XLLP_AC97_U14_FCSR1_M_FLAT    ( 0x00 << XLLP_AC97_U14_FCSR1_M_SHIFT )   // Flat mode
#define XLLP_AC97_U14_FCSR1_M_MIN1    ( 0x1 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Minimum mode
#define XLLP_AC97_U14_FCSR1_M_MIN2    ( 0x2 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Minimum mode
#define XLLP_AC97_U14_FCSR1_M_MAX     ( 0x3 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Maximum mode

#define XLLP_AC97_U14_FCSR1_TR_SHIFT  9   // 2 bits wide, Treble Boost

#define XLLP_AC97_U14_FCSR1_BB_SHIFT  11  // 4 bits wide, Bass Boost
// Bit 15 Reserved

// Feature Control/Status Register 2 (FCSR2) definitions

#define XLLP_AC97_U14_FCSR2_EV_SHIFT   0
#define XLLP_AC97_U14_FCSR2_EV_MASK    ( 0x7 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Mask for reading or clearing EV */
#define XLLP_AC97_U14_FCSR2_EV_NORMOP  ( 0x0 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for normal operation
#define XLLP_AC97_U14_FCSR2_EV_ACLPBK  ( 0x1 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for ACLink loopback
#define XLLP_AC97_U14_FCSR2_EV_BSLPBK  ( 0x2 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for bitstr loopback
#define XLLP_AC97_U14_FCSR2_EV_DACEVAL ( 0x3 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for DAC bitstr eval
#define XLLP_AC97_U14_FCSR2_EV_ADCEVAL ( 0x4 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for ADC bitstr eval
#define XLLP_AC97_U14_FCSR2_EV_CLKEVAL ( 0x5 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for Clocks eval mode
#define XLLP_AC97_U14_FCSR2_EV_ADC10EV ( 0x6 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for 10 bit ADC eval mode
#define XLLP_AC97_U14_FCSR2_EV_NORMOP1 ( 0x7 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for normal operation
// Bit 3 Reserved

#define XLLP_AC97_U14_FCSR2_SLP_SHIFT     4
#define XLLP_AC97_U14_FCSR2_SLP_MASK      ( 0x3 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Mask for reading or clearing SLP
#define XLLP_AC97_U14_FCSR2_SLP_NSLP      ( 0x0 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // No Smart Low Power Mode
#define XLLP_AC97_U14_FCSR2_SLP_SLPC      ( 0x1 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power Codec
#define XLLP_AC97_U14_FCSR2_SLP_SLPPLL    ( 0x2 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power PLL
#define XLLP_AC97_U14_FCSR2_SLP_SLPALL    ( 0x3 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power Codec & PLL
// Bits 6-15 Reserved

// Test Control Register (TCR) definitions
#define XLLP_AC97_U14_TCR_IDDQ    ( 0x1 << 0 )    // IDDQ testing
#define XLLP_AC97_U14_TCR_ROM     ( 0x1 << 1 )    // ROM testing
#define XLLP_AC97_U14_TCR_RAM     ( 0x1 << 2 )    // RAM testing
#define XLLP_AC97_U14_TCR_VOH     ( 0x1 << 3 )    // VOH testing
#define XLLP_AC97_U14_TCR_VOL     ( 0x1 << 4 )    // VOL testing
#define XLLP_AC97_U14_TCR_TRI     ( 0x1 << 5 )    // Tri-Sate testing
// Bits 7-15 Reserved

#define XLLP_AC97_U14_MAX_VOLUME    63
#define XLLP_AC97_U14_MAX_ADCGAIN   15

/*UCB1400 related functions*/
extern XLLP_ACODEC_ERROR_T XLLPUCBSetMasterVol(
                XLLP_ACODEC_CONTEXT_T *pDeviceContext, XLLP_UINT16_T GainInDb);
extern XLLP_ACODEC_ERROR_T XLLPUCBSetMasterInputGain(
                XLLP_ACODEC_CONTEXT_T *pDeviceContext, XLLP_UINT16_T GainInDb);
extern XLLP_ACODEC_ERROR_T XllpUCBGetInSampleRate(
                XLLP_ACODEC_CONTEXT_T *pDeviceContext, XLLP_UINT16_T * RateInHz);
extern XLLP_ACODEC_ERROR_T XllpUCBGetOutSampleRate (
                XLLP_ACODEC_CONTEXT_T *pDeviceContext, XLLP_UINT16_T * RateInHz);
extern XLLP_ACODEC_ERROR_T XllpUCBSetInSampleRate(
                XLLP_ACODEC_CONTEXT_T *pDeviceContext, XLLP_UINT16_T RateInHz);
extern XLLP_ACODEC_ERROR_T XllpUCBSetOutSampleRate (
                XLLP_ACODEC_CONTEXT_T *pDeviceContext, XLLP_UINT16_T RateInHz);
extern XLLP_ACODEC_ERROR_T XllpUCBEnterEquipmentState (
                XLLP_ACODEC_CONTEXT_T *pDeviceContext,
                XLLP_ACODEC_EQUIPMENT_T equipmentState);
extern XLLP_ACODEC_ERROR_T XllpUCBGetEquipmentState (
                XLLP_ACODEC_CONTEXT_T *pDeviceContext,
                XLLP_ACODEC_EQUIPMENT_T * pEquipmentState);
extern XLLP_ACODEC_ERROR_T XllpUCBSpecificInit (
                XLLP_ACODEC_CONTEXT_T *pDeviceContext);
extern XLLP_ACODEC_ERROR_T XllpUCBSpecificDeInit (
                XLLP_ACODEC_CONTEXT_T *pDeviceContext);

#endif
